1. Technical Field
The present disclosure relates to a voltage monitor semiconductor device for a storage device, a battery pack for a secondary battery, and an electronic device incorporating the battery pack. More particularly, the present disclosure relates to a voltage monitor semiconductor device to protect a lithium-ion battery, an electrical double-layer capacitor, or the like built into a secondary battery pack used in mobile electronic devices from abnormal conditions such as overcharge, over-discharge, and excess-current; a battery pack incorporating the semiconductor device; and an electronic device incorporating the battery pack.
2. Description of the Background Art
Typically, secondary batteries (rechargeable batteries) consisting of a high-capacity battery such as a lithium-ion battery have come to be widely used in portable electronic devices such as mobile phones. These portable electronic devices incorporate a battery pack having a charge-discharge detection circuit and/or an over-discharge detection circuit to protect the secondary battery. To control the charge and discharge of the secondary battery, there is generally employed a structure in which, in order to protect the secondary battery from being over-charged, over-discharged, or excess current, a protection switch is turned off after a given delay time when a detection terminal voltage equal to or higher than a predetermined level is detected, thereby prohibiting charging.
In addition, in known voltage monitor semiconductor devices, testing of integrated circuits (IC) or a substrate on which the IC is mounted is generally conducted by shortening the delay time, because the delay time for detecting abnormal state, for example, the overcharge, the over-discharge, and the excess current in a protection circuit is too long. This is accomplished, for example, by providing a test terminal and applying a voltage to the test terminal, to switch from a normal state to a test state.
For example, JP-3794547-B discloses a semiconductor device, serving as the charge-discharge protection circuit in the battery pack, that can shorten a test time using a test terminal, assure a long delay time, and changes from a detection state to a non-detection state when repetition of the detection state and non-detection state is necessary (when a tested circuit is included). More specifically, the charge-discharge protection circuit includes the test terminal, a comparator, and switching elements including two inverters whose thresholds are different from each other, a single NOR gate, and three NAND gates. The charge-discharge protection circuit can cause the delay time of the output of the comparator to switch among a normal delay mode, a delay mode shorten mode, and a non-delay time mode, by selecting three voltage levels Low, Medium, and High, as input of the test terminal, using the switching elements. In particular, a method in which the delay time is shortened by applying the voltage to the test terminal is disclosed.
In addition, in proposed in JP-2006-262574-A, a reduction technique to shorten the delay times of respective detection signals for a discharging excess current state and a charging excess current state, which has conventionally been used for testing, is used as the protection feature for normal charging and normal discharging. More specifically, in addition to a charging excess current detection circuit, a discharging excess current detection circuit, a delay circuit, and a discharging path shield circuit including a discharge control FET, a secondary battery protection circuit includes a reduction circuit and an error detection circuit. The reduction circuit shortens the delay time in the delay circuit. The error detection circuit detects that a voltage Vt of a charger negative terminal becomes higher than a preset threshold voltage Vh for detecting error discharging state that is much higher than a high threshold voltage in normal state Vh (Vt>>Vh) or becomes lower than a preset threshold voltage Vj for detecting error discharging state that is much lower than a low threshold voltage in the normal state Vj (Ve<<Vj). When the error detection circuit detects the error charging state or the error discharging state, the circuit is activated to quickly cut off the charging current path and the discharging current path. In particular, using the excess current detection terminal, the delay time from detection of the overcharge and the over-discharge to stopping charging and discharging to the secondary battery is shortened.
However, chip size increases if it is necessary to provide the test terminal, thereby increasing its cost. Alternatively, in a configuration in which the number of terminals in the circuit is limited, the test terminal cannot be provided. In order to solve this problem, in protection circuits having only the power supply terminal, voltage detection terminal, and the output terminal, it is a known technique to change the state from a normal state and latch it at a test state, by increasing the voltage at the power supply terminal to be a predetermined amount greater than the voltage at the voltage detection terminal or by inputting a pulse voltage to the power supply terminal.
JP-2007-228665-A proposes a charge-discharge protection circuit that can switch between a normal state and a test state without providing an external test terminal. More specifically, the charge-discharge protection circuit can switch between a normal state and the test state during which the charge-discharge control circuit is evaluated, based on whether or not an external voltage is supplied to the output terminal of the charge-discharge protection circuit used for the secondary battery. In addition, using a fuse, two test delay time reduction modes in the test state can be realized. In particular, the switch is made from the normal state to the test state by applying a voltage differing from the voltage in the normal state to the output terminal.
Alternatively, in JP-2007-195303-A, a charge-discharge control circuit that includes a delay circuit installed in an over-discharge detection circuit or an overcharge detection circuit can change the delay time in the detection circuits and shorten the test time, without providing a control terminal. More specifically, the charge discharge control circuit includes a voltage detection circuit that detects that a detection voltage exceeds a rated voltage between a power supply terminal of the charge-discharge control circuit and a power supply detection terminal. The delay time of the internal control circuit decreases based on the detection signal of the voltage detection circuit. In particular, when a difference between the voltage at the power supply terminal and the voltage at the voltage detection terminal exceeds a rated value, the switch is made from the normal state to the test state.
In addition, in JP-2008-61306-A, a charge-discharge control circuit includes a test circuit to switch between the normal state and the abnormal state, an overcharge detection circuit to receive a detection signal, and a delay circuit to set the delay time. In this circuit, after the test state, in order to reliably return to the normal state by releasing the test state, the delay circuit changes the delay time from the test state to the normal state in a state in which a predetermined time elapses after the test circuit is brought into the test state from the normal state, or in a state in which a predetermined time elapses after the overcharge detection circuit detects the detection signal in the test state. In particular, when the circuit mistakenly is brought into the test state because of external noise or the like, the normal state is resumed after a predetermined time has elapsed.
In above-described examples, in the protection circuits having only the power supply terminal, the voltage detection terminal, and the output terminal, it is known that the switch is made from the normal state and latched at the test state by increasing a voltage at the power supply terminal to be a predetermined amount greater than a voltage detection terminal or inputting a pulse voltage to the power supply terminal.
However, in these examples, in case in which the external noise outside of the IC mistakenly latches to the test state, a latch recovery countermeasure is required, which is complicated.